NXP Semiconductors /MIMXRT1021 /WDOG1 /WCR

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Interpret as WCR

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (WDZST_0)WDZST 0 (WDBG_0)WDBG 0 (WDE_0)WDE 0 (WDT_0)WDT 0 (SRS_0)SRS 0 (WDA_0)WDA 0 (SRE_0)SRE 0 (WDW_0)WDW 0 (WT_0)WT

WDW=WDW_0, WDZST=WDZST_0, WT=WT_0, SRS=SRS_0, WDE=WDE_0, WDA=WDA_0, SRE=SRE_0, WDT=WDT_0, WDBG=WDBG_0

Description

Watchdog Control Register

Fields

WDZST

WDZST

0 (WDZST_0): Continue timer operation (Default).

1 (WDZST_1): Suspend the watchdog timer.

WDBG

WDBG

0 (WDBG_0): Continue WDOG timer operation (Default).

1 (WDBG_1): Suspend the watchdog timer.

WDE

WDE

0 (WDE_0): Disable the Watchdog (Default).

1 (WDE_1): Enable the Watchdog.

WDT

WDT

0 (WDT_0): No effect on WDOG_B (Default).

1 (WDT_1): Assert WDOG_B upon a Watchdog Time-out event.

SRS

SRS

0 (SRS_0): Assert system reset signal.

1 (SRS_1): No effect on the system (Default).

WDA

WDA

0 (WDA_0): Assert WDOG_B output.

1 (WDA_1): No effect on system (Default).

SRE

software reset extension, an option way to generate software reset

0 (SRE_0): using original way to generate software reset (default)

1 (SRE_1): using new way to generate software reset.

WDW

WDW

0 (WDW_0): Continue WDOG timer operation (Default).

1 (WDW_1): Suspend WDOG timer operation.

WT

WT

0 (WT_0): - 0.5 Seconds (Default).

1 (WT_1): - 1.0 Seconds.

2 (WT_2): - 1.5 Seconds.

3 (WT_3): - 2.0 Seconds.

255 (WT_255): - 128 Seconds.

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